Comparing SOI vs. Silicon Wafers: What’s Best for Your Semiconductor Project?

1 Introduction

SOI is a semiconductor material with a layered silicon layer-insulating layer-silicon substrate structure. Compared with silicon wafers, which are commonly used in semiconductor devices, there are significant differences between the two in terms of material structure, performance characteristics application areas, etc.

The SOI structure improves the performance and reliability of the device through the layered silicon layer-insulating layer-silicon substrate structure, but the manufacturing cost is higher. The traditional silicon wafers, on the other hand, have lower manufacturing costs and are suitable for a wide range of integrated circuit manufacturing.

2 What is SOI?

SOI stands for Silicon-On-Insulator. In SOI, the surface of a silicon chip is covered with an insulating material (usually silicon dioxide), on which a silicon layer is then grown. This structure creates a silicon layer-insulating layer-silicon substrate layered structure.

2.1 The Structure of SOI

The structure of an SOI (Silicon-On-Insulator) consists of the following major parts:

1. Si Layer: On top of the SOI structure is a layer of silicon (Si) crystals that typically have the desired electronic properties and device characteristics. This layer can be prepared using standard silicon wafer growth techniques.
2. Insulating Layer: Below the Si layer is an insulating material, usually silicon dioxide (SiO2). The purpose of the insulating layer is to isolate the silicon layer above from the silicon substrate below, thereby reducing crosstalk between transistors.
3. Silicon Substrate: The silicon substrate is the bottom of the SOI structure and is usually the main support substrate for the wafer. The silicon substrate is usually crystalline silicon, which provides mechanical support and stability to the SOI structure.

2.2 The Classification of SOI

There are several different variants of SOI technology. SOIs can be categorized according to different criteria, depending on their structure as well as their purpose.

2.2.1 Classification by Type of Structure

Common SOI (c-SOI): Common SOI is one of the most common SOI structures, also known as full SOI. it utilizes the common SOI fabrication method of depositing an insulating layer (usually silicon dioxide) on the surface of a silicon wafer, and then growing a silicon layer on top of it. In a common SOI, the thickness of the silicon layer is usually comparable to the thickness of the insulating layer, forming a silicon layer-insulating layer-silicon substrate structure.

Partial SOI (p-SOI): Partial SOI differs from regular SOI in that the thickness of the silicon layer is thinner, only a fraction of the thickness of the insulating layer. In a partial SOI, the thickness of the silicon layer is typically less than the thickness of the insulating layer, giving the partial SOI structure a thinner silicon layer.

Reverse SOI (r-SOI): Reverse SOI is a special SOI structure that is different from normal SOI and partial SOI. In reverse SOI, the silicon layer is removed from the substrate and reattached to the insulating layer. This structure allows the transistor to be located above the insulating layer and the silicon substrate to be located below the insulating layer, thus changing the topology of the conventional SOI structure.

These different SOI variants offer different advantages and applicability in specific applications. Common SOIs are commonly used in high-performance and low-power applications, while partial SOIs are more suitable for some specific radio frequency (RF) device fabrications, and inverted SOIs offer additional benefits in specific applications, such as high-speed, low-loss devices.

2.2.2 Classification by Crystal Substrate Type

Silicon-on-Insulator (SIMOX-SOI): SIMOX (Separation by IMplantation of OXygen) is a common method of SOI preparation, also known as silicon-on-insulator. In SIMOX-SOI preparation, oxygen ions are injected into the wafer and then heat-treated to cause the oxygen ions to form an insulating layer of silicon oxide in the wafer, resulting in the formation of the SOI structure.

Ultra-Thin SOI (UTSOI): Ultra-Thin SOI is a special type of SOI structure characterized by a very thin silicon layer, typically between a few nanometers and tens of nanometers. The preparation method of UTSOI usually involves special growth or stripping techniques to form a very thin silicon layer on a silicon substrate to realize the SOI structure.

Epitaxial SOI (Epi-SOI): Epi-SOI is a method of forming SOI structures by growing an epitaxial silicon layer on a silicon substrate. In Epi-SOI, the epitaxial silicon layer is grown on a silicon substrate and typically has the same crystal structure as the substrate, but with an insulating layer between the silicon layer and the substrate.

SIMOX-SOI is commonly used in IC fabrication, UTSOI is commonly used for high-performance and low-power applications such as mobile communications and RF devices, while Epi-SOI provides better crystal quality and structural control for specific device fabrication needs.

2.2.3 Classification by the Thickness of the Silicon Layer

Thin-Film SOI: In Thin-Film SOI, the thickness of the silicon layer is usually between tens of nanometers and hundreds of nanometers. This type of SOI structure is often used to fabricate ultra-thin devices, such as low-power electronic devices, optoelectronic devices, and so on. Thin-layer SOIs are typically prepared using a series of precision processing steps, including techniques such as chemical mechanical polishing (CMP) and hydrogen ion injection and stripping.

Thick-Film SOI: In thick-film SOI, the thickness of the silicon layer is typically several hundred nanometers or more. This type of SOI structure is typically used to fabricate traditional integrated circuit devices such as microprocessors, memories, etc. Thick-layer SOIs are usually prepared using different techniques such as SIMOX, Unibond, and Smart Cut. These techniques allow the preparation of silicon layers with large thicknesses to meet the needs of conventional integrated circuit manufacturing.

2.2.4 Classification by the Charge Control Method for Transistors

Fully Depleted SOI (FD-SOI): In FD-SOI, the entire silicon layer is in a depleted state, which means that the transistor's charge is completely controlled by the gate above and is not affected by the bottom substrate. By precisely controlling the thickness of the silicon layer and the characteristics of the insulating layer, it is possible to achieve an entire silicon layer in a depleted state. This structure provides better charge control and lower leakage current. Fully depleted SOI is often regarded as a next-generation semiconductor technology with higher performance and lower power consumption and is therefore receiving more and more attention in chip design and fabrication.

Partially depleted SOI (pFD-SOI): In partially depleted SOI, a part of the silicon layer is in a depleted state while another part remains in a non-depleted state. Typically, with proper design and process, it is possible to realize that only a portion of the silicon layer (usually the upper portion) is in a depleted state. Partially depleted SOI can be used in high-performance and low-power applications such as mobile communications, radio frequency (RF) devices, and other areas. It offers opportunities for better charge control and performance optimization.

The table below showcases the various SOI structures, their defining characteristics, and their typical applications, providing a comprehensive overview of the differences between each type of SOI.

Stanford Advanced Materials (SAM) and other reliable suppliers offer SOI Wafers of various sizes and types. These choices are tailored to meet your precise specifications.

Table 1 Comparison of Different Types of SOI Wafers

3 SOI versus Silicon Wafers, Which Are Better?

Silicon-on-Insulator (SOI) technology and traditional silicon wafers have long been pivotal in shaping the landscape of semiconductor manufacturing, each possessing distinct structural attributes and performance capabilities. As the demand for more efficient, faster, and smaller electronic devices grows, understanding the differences between these two foundational materials becomes crucial. This comparison seeks to highlight the structural nuances and performance outcomes of SOI and silicon wafers.

3.1 How SOI and Silicon Wafers Differ in Structure

Silicon Wafer: A conventional silicon wafer consists of a single silicon crystal and a monocrystalline silicon structure. In a traditional silicon wafer, the surface of the wafer is usually a single crystal of silicon with no additional insulating layer. Silicon wafers have a simple structure and are the most common substrate for semiconductor devices.

SOI: In the SOI structure, the surface of the silicon wafer is covered with a layer of insulating material (usually silicon dioxide). This layer of insulating material is commonly used to isolate the silicon layer from the silicon substrate, thereby reducing crosstalk between devices and improving device performance and reliability. On top of the insulating layer, another silicon layer is grown to form a layer structure of silicon layer-insulating layer-silicon substrate. The silicon layer is the active layer of the transistor and usually has the desired electronic properties and device performance. The thickness of the insulating layer can be adjusted according to the application requirements to control the device's characteristics and performance.

SOIs have an additional insulating layer compared to conventional silicon wafers. The presence of this insulating layer improves device performance and reliability but also increases the complexity and cost of fabrication.

3.2 How SOI and Silicon Wafers Differ in Performance

1. Crosstalk suppression: Each transistor in the SOI structure is isolated by an insulating layer, significantly reducing crosstalk effects between devices. Due to the presence of the insulating layer, the electromagnetic coupling effect between the transistors is reduced, which improves the performance and reliability of the device. Crosstalk is usually a serious problem in high-density integrated circuits, and the use of SOIs effectively reduces the effect of crosstalk on device performance.
2. Speed and power advantages: SOI devices typically have higher speed and lower power efficiency. Due to the reduced resistance to charge movement in the SOI structure, electrons in the silicon layer can move faster, resulting in higher switching speeds and lower power consumption. This gives SOI a clear advantage in high-performance and low-power applications, such as mobile communications and high-performance computing.
3. Improved radiation resistance: The SOI structure improves the radiation resistance of the device, making it more suitable for applications in high-radiation environments. Due to the presence of an insulating layer, SOI devices are less sensitive to radiation and therefore have a wide range of applications in space, nuclear power plants, and other electronic devices in high-radiation environments. The improved radiation resistance is crucial for some specific applications such as space aerospace and nuclear energy.

3.3 How SOI and Silicon Wafers Are Used

--SOI Application Areas

High-performance applications: SOI is often used in applications that require high performance, such as high-speed computer chips and graphics processors. Its low charge motion impedance and crosstalk suppression characteristics make it ideal for realizing high performance.

Low-power applications: Because SOI devices have lower power consumption and higher switching speeds, they have a wide range of applications in areas such as mobile devices and wireless sensor networks that require low power consumption. For example, chips in devices such as smartphones and tablet PCs often utilize SOI technology.

Radio Frequency (RF) applications: SOI's high speed and low loss characteristics give it a huge advantage in Radio Frequency (RF) applications. For example, SOI devices can be used to fabricate high-performance RF front-end modules, antenna switches, power amplifiers, and more.

Applications in high-radiation environments: The SOI structure improves the radiation resistance of the device, which makes it important for applications in space, nuclear power plants, and other high-radiation environments. For example, space probes, satellite communication systems, and other devices that need to work in a high-radiation environment often use SOI technology.

--Traditional Silicon Wafer Applications

Traditional silicon wafers are widely used in the manufacture of various integrated circuits, including microprocessors, memories, sensors, and so on. Silicon wafers are the basis for manufacturing integrated circuits (ICs). Various types of ICs, including microprocessors, memories, analog circuits, digital circuits, etc., are manufactured by layering different materials and circuits on silicon wafers. Almost all electronic devices will use traditional silicon wafer manufacturing chips, such as personal computers, home appliances, and automotive electronic systems. It can also be used to manufacture a variety of electronic devices commonly used in industrial fields, solar cells, and biomedical devices. Due to the excellent semiconductor properties, as well as mature production processes and stable quality control, silicon wafers are widely used in production and research processes, and the technological threshold is also lower compared to SOI.

3.4 How SOI and Silicon Wafers Are Produced

--SOI Crystal Preparation Methods

3.4.1 SIMOX Technology

SIMOX technology, short for Separation by IMplantation of OXygen, stands as one of the pioneering methods for preparing SOI (Silicon-On-Insulator) wafers. This technique leverages ion implantation to introduce oxygen ions into silicon, forming a buried oxide isolation layer. This buried oxide layer effectively isolates the substrate from the top silicon thin film layer. The process involves injecting oxygen ions into the silicon wafer below the surface, typically at an energy level of 200 keV and a dose of 1.8 × 10^18 cm^-2. Subsequently, a high-temperature annealing process lasting 3 to 6 hours at 1350°C facilitates chemical reactions between the oxygen ions and silicon atoms within the wafer, resulting in the formation of a silicon dioxide insulating layer with a thickness of less than 240 nm beneath the surface. Above this insulating layer, a crystalline silicon layer forms, resulting in the SOI structure comprising silicon thin film - silicon dioxide insulating layer - silicon substrate.

Advantages of SIMOX technology include the formation of a relatively uniform Buried Oxide (BOX) layer. The thickness of the silicon layer atop the BOX can be precisely controlled by managing the injection energy. Moreover, the interface between the BOX and the top silicon layer remains remarkably flat.

However, SIMOX technology does have its limitations. The range for adjusting the thickness of the BOX and the top silicon layer is relatively limited. Typically, the BOX thickness does not exceed 240 nm, as excessively thin layers may lead to breakdown between the top layer and the substrate, accompanied by increased parasitic capacitance. Similarly, the top silicon film thickness is usually limited to 300 nm, necessitating costly epitaxial silicon growth and subsequent chemical mechanical polishing (CMP) flattening treatment. Additionally, SIMOX may induce surface film damage, and the crystal quality of the top silicon film may not match that of bulk single-crystal silicon. Moreover, the crystal quality of the buried SiO2 is inferior to that achieved through thermal oxidation. The implementation of SIMOX requires specialized ion implantation equipment, such as expensive large-beam-flow oxygen injection machines, along with prolonged high-temperature annealing processes, contributing to higher production costs.

3.4.2 BESOI Technology

BESOI (Bond and Etch Back Silicon-On-Insulator) technology involves bonding two wafers closely together, creating a silicon dioxide layer as the buried oxide layer between them. Subsequently, back-engraving technology is employed to precisely adjust the thickness of one wafer to form the desired thickness for the SOI wafers.

The BESOI process begins by treating one wafer (wafer A) with thermal oxidation, creating an oxide layer, while the other wafer (wafer B) undergoes low-temperature bonding with the oxidized surface of wafer A. This bonding process, known as Silicon Fusion Bonding (SFB), involves several steps:

Hydrophilic Treatment: Both wafers undergo a low-temperature (400°C) hydrophilic treatment to induce the formation of hydroxyl (OH) bonds on their surfaces.

Bonding through Van der Waals Force: The two wafers are then brought into contact, and the OH bonds facilitate their bonding through Van der Waals force.

Thermal Annealing: High-temperature (1100°C) thermal annealing is conducted to drive away hydrogen ions, promoting the formation of Si-O-Si bonds at the bonded interface, thereby reinforcing the bonding.

Back-etching: Excess silicon from one wafer is removed using back-engraving technology, leaving behind the desired thickness for the top silicon thin film. Subsequent annealing and chemical mechanical polishing (CMP) ensure the formation of a smooth and clean surface for the SOI wafers.

BESOI technology offers several advantages over SIMOX technology. For instance, it avoids issues related to injection damage and ensures the formation of a thermally oxidized buried oxide layer with lower defect density and pinhole density. Additionally, the top silicon film produced through BESOI consists of high-quality single-crystal silicon, enhancing overall device performance.

However, BESOI technology also presents challenges. It is difficult to achieve very thin top silicon films, and controlling interface defects and the homogeneity of the top silicon film remains a challenge. Moreover, the process involves high-cost back-engraving and CMP steps, leading to significant wafer material wastage, which cannot be recycled and contributes to higher production costs.

3.4.3 Smart-Cut technology

Smart-Cut technology is derived from BESOI: two silicon wafers are prepared first; one of the wafers is thermally oxidized to form a layer of SiO2, and then hydrogen ions are injected into the wafer substrate; the other wafer does not need to be processed; similar to BESOI, the two wafers are bonded together; after bonding, the hydrogen-ion injected wafers break up at the hydrogen-ion enriched interface by a thermal reaction at 400-600 °C; finally, the interface between the broken surface and the oxide layer forms a silicon film layer after high-temperature treatment (1100 °C) to drive away the hydrogen ions. After bonding, the wafers injected with hydrogen ions will fracture at the hydrogen ion enrichment point, and a silicon thin film layer will be formed between the fracture surface and the oxide layer; finally, after high-temperature treatment (1100°C), the hydrogen ions are driven out, so that the bonded interface will form a Si-O-Si bond, which will strengthen the chemical bonding, and improve the quality of the silicon thin film layer, and then the surface will be flattened by CMP treatment.

Smart-Cut is similar to BESOI in that the top silicon film is bulk silicon and the BOX is a thermally oxidized film. The thickness of the BOX layer and the top silicon film can be adjusted over a wide range, and the thickness of the top silicon film is controlled by utilizing the energy of the ion implantation so that the top silicon film with very thin thickness and good uniformity can be obtained. In addition, the stripped wafer material can be reused, thus enabling cost reduction.

--Silicon Wafer Crystal Preparation Method

The Czochralski method is widely employed for growing silicon crystals, leveraging a crucible filled with silicon heated to maintain a temperature of 1685°C. This temperature exceeds the melting point of silicon by about 100°C, rendering the silicon in the crucible molten. Within the upper part of the crucible, a lifting rod is situated, featuring a mechanical device enabling it to lift and rotate freely. A small piece of monocrystalline silicon, acting as a "seed," is affixed atop the lever. This seed crystal initiates the attraction of surrounding silicon atoms, organizing them into a crystal structure. As the crystal gradually ascends and rotates, the extracted sections remain part of the same single crystal. The resulting large single crystal measures up to 200 millimeters in diameter, thicker than an average arm. This crystal exhibits no interfaces or defects, epitomizing the utmost perfection attainable in human-made single crystals.

To ensure material purity and prevent non-uniform nucleation, all operations must occur under vacuum or inert gas protection. Traditional single-crystal silicon lifting techniques involve initiating a thin neck at the onset of crystal growth, termed the "necking method," to prevent crystal dislocations. However, advancements in seeding technology, particularly the infusion of a significant amount of boron into the seed crystal, have dramatically bolstered its strength, obviating the need for a 3 mm diameter neck. This innovative approach supersedes the three-decade-old necking method, not only facilitating the production of large single-crystal silicon but also shortening crystal growth times and enhancing yields, thus opening up possibilities for the cost-effective production of ultra-large-scale integrated circuits.

In wafer growth, polysilicon is introduced into a quartz crucible within a furnace, followed by vacuum or inert gas purging to create a molten state. Once the molten silicon stabilizes, single crystals can be pulled using a pre-determined seed crystal's internal crystal direction as a guide on the liquid surface. Through precise control of the crucible liquid surface height, solid-liquid interface temperature, and seed crystal rotation speed, silicon is transformed from liquid back into solid, ensuring uniform internal crystalline direction for the growth of large-diameter single crystals. Computer-controlled automatic adjustment processes and lifting speeds guarantee isotropic monocrystalline silicon growth.

Table 2 SOI Wafers Vs. Silicon Wafers

4 Conclusion

There are significant differences between SOI and silicon wafers in terms of material structure, performance characteristics application areas, etc. The SOI structure improves device performance and reliability through a layered silicon layer-insulating layer-silicon substrate structure but at a higher manufacturing cost. In contrast, traditional silicon wafer manufacturing is less expensive and suitable for a wide range of integrated circuit manufacturing. Therefore, when selecting a material structure, the advantages and disadvantages of SOI and silicon wafers should be comprehensively evaluated based on specific application requirements and cost considerations to achieve the best performance and economic benefits.

Related Reading:

The Impact of Silicon Wafer Quality on Semiconductor Performance and Reliability

References:

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[2]Xin F ,Jiaqi N ,Shanglin Y , et al. Optical notch filters with tunable central wavelength and reconfigurable free spectral range on SOI platform[J]. Optics Communications,2024,554.

[3]N. V ,A. M ,I. K , et al. Novel crossbar array of silicon nitride resistive memories on SOI enables memristor rationed logic[J]. Solid State Electronics,2024,211.